The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the semiconductor industry utilized various methods to form the gate of MOS transistors. One particular technique formed a trench within a semiconductor substrate and formed the gate material within the trench. The gate material was recessed below the surface of the semiconductor substrate in order to provide a planar surface for building other portions of the transistor. Such a method is disclosed in U.S. Pat. No. 5,034,785 issued to Richard Blanchard on Jul. 23, 1991. One problem with such techniques was the resistance of the gate. The resistance of the gate of such transistors was sufficiently high to limit the switching speed of the transistor thereby limiting the applications in which the transistors were used. Another limitation was the gate-to-source capacitance. The source typically extended to a large depth into the substrate thereby forming a large surface area along the gate oxide. This large surface area resulted in a large gate-to-source capacitance that further limited the switching speed.
Accordingly, it is desirable to have a method of forming a semiconductor device that results in a low gate resistance and a low gate-to-source capacitance.